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Lattice Semiconductor
10Gb Ethernet XGXS IP Core User’s Guide
I/O Signal Descriptions
Table 10. XGXS Solution I/O
Signal Name
Direction
Description
XGMII Signals
xgmii_tx_data[31:0]
input
32-bit wide DDR XGMII input data.
xgmii_tx_ctrl[3:0]
input
Per-byte DDR XGMII control inputs.
xgmii_txclk_156
input
156MHz XGMII transmit (XGXS input) clock.
xgmii_rx_data[31:0]
output
32-bit wide DDR XGMII output data.
xgmii_rx_ctrl[3:0]
output
Per-byte DDR XGMII control outputs.
xgmii_rxclk_156
input
XGMII receive (XGXS output) reference clock.
xgmii_rxclk_156_out
output
Forwarded XGMII receive (XGXS output) clock.
XAUI Signals
HDINN_BA
input
High-speed CML receive data input - SERDES quad B, channel A.
HDINP_BA
input
High-speed CML receive data input - SERDES quad B, channel A.
HDINN_BB
input
High-speed CML receive data input - SERDES quad B, channel B.
HDINP_BB
input
High-speed CML receive data input - SERDES quad B, channel B.
HDINN_BC
input
High-speed CML receive data input - SERDES quad B, channel C.
HDINP_BC
input
High-speed CML receive data input - SERDES quad B, channel C.
HDINN_BD
input
High-speed CML receive data input - SERDES quad B, channel D.
HDINP_BD
input
High-speed CML receive data input - SERDES quad B, channel D.
HDOUTN_BA
output
High-speed CML transmit data output - SERDES quad B, channel A.
HDOUTP_BA
output
High-speed CML transmit data output - SERDES quad B, channel A.
HDOUTN_BB
output
High-speed CML transmit data output - SERDES quad B, channel B.
HDOUTP_BB
output
High-speed CML transmit data output - SERDES quad B, channel B.
HDOUTN_BC
output
High-speed CML transmit data output - SERDES quad B, channel C.
HDOUTP_BC
output
High-speed CML transmit data output - SERDES quad B, channel C.
HDOUTN_BD
output
High-speed CML transmit data output - SERDES quad B, channel D.
HDOUTP_BD
output
High-speed CML transmit data output - SERDES quad B, channel D.
REFCLKP_B
input
SERDES Quad B reference clock.
REFCLKN_B
input
SERDES Quad B reference clock.
Please refer to the ORT82G5 Data Sheet for additional information on con?guring the SERDES interface for speci?c applica-
tions.
MDIO Interface Signals
mdio
input/output
MDIO bi-directional data.
mdc
input
MDIO clock.
XGXS Soft IP Control and Status Signals
reset_n
input
XGXS programmable core reset (active low).
pwrup_init_en
input
Enable automatic con ? guration of embedded core (active high - see Sec. 2.7
for details).
inj_err_n
input
Inject error (active low - see Sec. 2.6 for details).
ORT82G5 Embedded Core Control, Global I/O and FPGA Con ? guration I/O
Please refer to the ORCA Series 4 FPGA Data Sheet and the ORT82G5 Data Sheet for information on the various con?gura-
tion options.
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